File:DARPA SyNAPSE 16 Chip Board.jpg
A circuit board with a 4×4 array of SyNAPSE-developed chips. Each chip has one million electronic “neurons” and 256 million electronic synapses between neurons. Built on 28nm process technology, the 5.4 billion transistor chip has one of the highest transistor counts of any chip ever produced as of 2014.

SyNAPSE is a DARPA program that aims to develop electronic neuromorphic machine technology that scales to biological levels. More simply stated, it is an attempt to build a new kind of cognitive computer with similar form, function, and architecture to the mammalian brain. Such artificial brains would be used in robots whose intelligence would scale with the size of the neural system in terms of total number of neurons and synapses and their connectivity.

SyNAPSE is a backronym standing for Systems of Neuromorphic Adaptive Plastic Scalable Electronics. The name alludes to synapses, the junctions between biological neurons. The program is being undertaken by HRL Laboratories (HRL), Hewlett-Packard, and IBM Research. In November 2008, IBM and its collaborators were awarded $4.9 million in funding from DARPA while HRL and its collaborators were awarded $5.9 million in funding from DARPA. For the next phase of the project, DARPA added $16.1 million more to the IBM effort while HRL received an additional $10.7 million. In 2011, DARPA added $21 million more to the IBM project.[1] and an additional $17.9 million to the HRL project.[2] The SyNAPSE team for IBM is led by Dharmendra Modha, manager of IBM's cognitive computing initiative. The SyNAPSE team for HRL is led by Narayan Srinivasa, manager of HRL's Center for Neural and Emergent Systems.[3]

The initial phase of the SyNAPSE program developed nanometer scale electronic synaptic components capable of adapting the connection strength between two neurons in a manner analogous to that seen in biological systems (Hebbian learning), and simulated the utility of these synaptic components in core microcircuits that support the overall system architecture.

Continuing efforts will focus on hardware development through the stages of microcircuit development, fabrication process development, single chip system development, and multi-chip system development. In support of these hardware developments, the program seeks to develop increasingly capable architecture and design tools, very large-scale computer simulations of the neuromorphic electronic systems to inform the designers and validate the hardware prior to fabrication, and virtual environments for training and testing the simulated and hardware neuromorphic systems.

Published product highlights

  • clockless operation (event-driven), consumes 70 mW during real-time operation, power density of 20 mW/cm²[4]
  • manufactured in Samsung’s 28 nm process technology, 5.4 billion transistors
  • one million neurons and 256 million synapses networked into 4096 neurosynaptic cores by a 2D array, all programmable
  • each core module integrates memory, computation, and communication, and operates in an event-driven, parallel, and fault-tolerant fashion


The following people and institutions are participating in the DARPA SyNAPSE program:[5]

IBM team

HRL Team

See also


External links