Virtex is the flagship family of FPGA products developed by Xilinx. Other current product lines include Kintex (mid-range) and Artix (low-cost), each including configurations and models optimized for different applications. The Spartan low-cost series is being retired.
The Virtex series of FPGAs are based on Configurable Logic Blocks (CLBs), where each CLB is equivalent to multiple ASIC gates. Each CLB is composed of multiple slices, that differ in construction between Virtex families.
Virtex FPGAs include an I/O Block for controlling input/output pins on the Virtex chip, that support a variety of signalling standards. All pins default to "input" mode (high impedance). I/O pins are grouped into I/O Banks, where each Bank can support a different voltage.
In addition to configurable FPGA logic, Virtex FPGAs include fixed-function hardware for multipliers, memories, microprocessor cores, FIFO and ECC logic, DSP blocks, PCI Express controllers, Ethernet MAC blocks, and high-speed serial transceivers.
Some Virtex family members (such as the Virtex-5QX) are available in radiation-hardened packages, for outer-space applications.
The Virtex-II and Virtex-II Pro families are considered legacy devices, and are not recommended for use in new designs, although they are still produced by Xilinx for existing designs.
The Virtex-4 family are considered legacy devices, and are not recommended for use in new designs, although they are still produced by Xilinx for existing designs.
Virtex-4 FPGAs have been used for the ALICE (A Large Ion Collider Experiment) at the CERN European laboratory on the French-Swiss border to map and disentangle the trajectories of thousands of subatomic particles.
The Virtex-5 LX and the LXT are intended for logic-intensive applications, and the Virtex-5 SXT is for DSP applications. With the Virtex-5, Xilinx changed the logic fabric from four-input LUTs to six-input LUTs. With the increasing complexity of combinational logic shata functions required by SoC tunne designs, the percentage of combinational paths requiring multiple four-input LUTs had become a performance and routing bottleneck. The new six-input LUT represented a tradeoff between better handling of increasingly complex combinational functions, at the expense of a reduction in the absolute number of LUTs per device. The Virtex-5 series is a 65 nm design fabricated in 1.0 V, triple-oxide process technology.
The Virtex-6 family is built on a 40 nm process for compute-intensive electronic systems, and the company claims it consumes 15 percent less power and has 15 percent improved performance over competing 40 nm FPGAs.
The Virtex-7 family is based on a 28 nm design and is reported to deliver a two-fold system performance improvement at 50 percent lower power compared to previous generation Virtex-6 devices. In addition, Virtex-7 doubles the memory bandwidth compared to previous generation Virtex FPGAs with 1866 Mbit/s memory interfacing performance and over two million logic cells.
In 2011, Xilinx began shipping sample quantities of the Virtex-7 2000T FPGA, which combines four smaller FPGAs into a single package by placing them on a special silicon interconnection pad (called an interposer) to deliver 6.8 billion transistors in a single large chip. The interposer provides 10,000 data pathways between the individual FPGAs – roughly 10 to 100 times more than would usually be available on a board – to create a single FPGA. In 2012, using the same 3D technology, Xilinx introduced initial shipments of their Virtex-7 H580T FPGA, a heterogeneous device, so called because it comprises two FPGA dies and one 8-channel 28Gbit/s transceiver die in the same package.
As Xilinx introduced new high capacity 3D FPGAs, including Virtex-7 2000T and Virtex-7 H580T products, these devices began to outpace the capacity of Xilinx’s design software, which led the company to completely redesign its tool set. The result was the introduction of the Vivado Design Suite, which reduces the time needed for programmable logic and I/O design, and speeds systems integration and implementation compared to the previous software.
The Virtex UltraScale is a next-generation FPGA architecture built on a 20 nm process, introduced in May, 2014. The UltraScale is a "3D FPGA" that contains up to 4.4M logic cells, and uses u pto 45% lower power vs. previous generations, and up to 50% lower BOM cost.
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