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XOR gate

This article is about XOR in the sense of an electronic logic gate (e.g. CMOS 4030). For XOR in the purely logical sense, see Exclusive disjunction. For other uses, see XOR (disambiguation).
0 0 0
0 1 1
1 0 1
1 1 0

The XOR gate (sometimes EOR gate, or EXOR gate and pronounced as Exclusive OR gate) is a digital logic gate that implements an exclusive or; that is, a true output (1/HIGH) results if one, and only one, of the inputs to the gate is true. If both inputs are false (0/LOW) or both are true, a false output results. XOR represents the inequality function, i.e., the output is true if the inputs are not alike otherwise the output is false. A way to remember XOR is "one or the other but not both".

XOR can also be viewed as addition modulo 2. As a result, XOR gates are used to implement binary addition in computers. A Half adder consists of an XOR gate and an AND gate. Other uses include substractors, comparators, and controlled inverters.[1]

The algebraic expressions <math>A \cdot \overline{B} + \overline{A} \cdot B</math> and <math>(A + B) \cdot </math> ( <math> \overline A + \overline B </math> ) both represent the XOR gate with inputs A and B. The behavior of XOR is summarized in the truth table shown on the right.


There are two symbols for XOR gates: the traditional symbol and the IEEE symbol. For more information see Logic Gate Symbols.

File:XOR ANSI.svg
Traditional XOR Symbol
File:XOR IEC.svg

The logic symbols ⊕ and can be used to denote XOR in algebraic expressions.

C-like languages use the caret symbol ^ to denote bitwise XOR. (Note that the caret does not denote logical conjunction (AND) in these languages, despite the similarity of symbol.)


If a specific type of gate is not available, a circuit that implements the same function can be constructed from other available gates. A circuit implementing an XOR function can be trivially constructed from an XNOR gate followed by a NOT gate. If we consider the expression <math>A \cdot \overline{B} + \overline{A} \cdot B</math>, we can construct an XOR gate circuit directly using AND, OR and NOT gates. However, this approach requires five gates of three different kinds.

An XOR gate circuit can be made from four NAND or five NOR gates in the configurations shown below . In fact, both NAND and NOR gates are so-called "universal gates," and any logical function can be constructed from either NAND logic or NOR logic alone.

As an alternative, if different gates are available we can apply Boolean algebra to transform <math>A \cdot \overline{B} + \overline{A} \cdot B \equiv (A + B) \cdot </math> ( <math> \overline A + \overline B </math>) as stated above, and apply de Morgan's Law to the last term to get <math>(A + B) \cdot </math> <math> \overline {(A \cdot B)} </math> which can be implemented using only three gates as shown below.

File:XOR from NAND.svg
XOR gate circuit constructed using only NAND gates.
File:XOR from NOR.svg
XOR gate circuit constructed using only NOR gates.
File:254px 3gate XOR.jpg
XOR gate circuit using three mixed gates

More than two inputs

Strict reading of the definition of exclusive or, or observation of the IEC rectangular symbol, raises the question of correct behaviour with additional inputs. If a logic gate were to accept three or more inputs and produce a true output if exactly one of those inputs were true, then it would in effect be a one-hot detector (and indeed this is the case for only two inputs). However, it is rarely implemented this way in practice.

It is most common to regard subsequent inputs as being applied through a cascade of binary exclusive-or operations: the first two signals are fed into an XOR gate, then the output of that gate is fed into a second XOR gate together with the third signal, and so on for any remaining signals. The result is a circuit that outputs a 1 when the number of 1s at its inputs is odd, and a 0 when the number of incoming 1s is even. This makes it practically useful as a parity generator or a modulo-2 adder.

For example, the 74LVC1G386 microchip is advertised as a three-input logic gate, and implements a parity generator.[2]


Uses in addition

The XOR logic gate can be used as a one-bit adder that adds any two bits together to output one bit. For example, if we add 1 plus 1 in binary, we expect a two-bit answer, 10 (i.e. 2 in decimal). Since the trailing sum bit in this output is achieved with XOR, the preceding carry bit is calculated with an AND gate. This is the main principle in Half Adders and the combined AND-XOR circuit may be chained together in order to add ever longer binary numbers.
File:Half Adder.svg
Example half adder circuit diagram

Pseudo-random number generation

Pseudo-random number (PRN) generators, specifically Linear feedback shift registers, are defined in terms of the exclusive-or operation. Hence, a suitable setup of XOR gates can model a linear feedback shift register, in order to generate random numbers.

Correlation and sequence detection

XOR gates produce a 0 when both inputs match. When searching for a specific bit pattern or PRN sequence in a very long data sequence, a series of XOR gates can be used to compare a string of bits from the data sequence against the target sequence in parallel. The number of 0 outputs can then be counted to determine how well the data sequence matches the target sequence. Correlators are used in many communications devices such as CDMA receivers and decoders for error correction and channel codes. In a CDMA receiver, correlators are used to extract the polarity of a specific PRN sequence out of a combined collection of PRN sequences.

A correlator looking for 11010 in the data sequence 1110100101 would compare the incoming data bits against the target sequence at every possible offset while counting the number of matches (zeros):

1110100101 (data)
11010      (target)
00111      (XOR) 2 zero bits

 00000     5 zero bits

  01110    2 zero bits

   10011   2 zero bits

    01000  4 zero bits

     11111 0 zero bits

Matches by offset:

  :     :
: : : : :  
0 1 2 3 4 5

In this example, the best match occurs when the target sequence is offset by 1 bit and all five bits match. When offset by 5 bits, the sequence exactly matches its inverse. By looking at the difference between the number of ones and zeros that come out of the bank of XOR gates, it is easy to see where the sequence occurs and whether or not it is inverted. Longer sequences are easier to detect than short sequences.

See also

External links

  • Interactive XOR Gate, Demonstrate the logic flow of the XOR Gate circuit created with Teahlab's simulator.


  1. ^ Fletcher, William (1980). An engineering approach to digital design. Prentice-Hall. p. 98. ISBN 0-13-277699-5. 
  2. ^ 74LVC1G386 data sheet
sv:Disjunktion (logik)#OR-grind och XOR-grind